The present invention relates to the demodulation of frequency modulated (FM) signals and, more specifically, it relates to a complex valued delta sigma phase locked loop (PLL) demodulator.
Current mobile telephone handsets need to conserve as much power a possible to extend their battery life. Unfortunately, current FM demodulation techniques used in these handsets require multiple discrete components to implement. The multiplicity of these components leads to high power consumption and consequently, to shorter battery life. A single-chip demodulator would have lower power consumption and, theoretically, lead to longer battery life.
However, a single-chip demodulator is not the only requirement for the mobile handsets of the future. The demodulator must also provide some of the selectivity required in the receiver while simultaneously extracting the analogue FM information from the input IF signal. This is particularly important given the Advanced Mobile Phone System (AMPS)requirement for the demodulator to work properly with an interferer on the alternate channel only 60 kHz away from the desired signal on the assigned channel. The AMPS specification requires the receiver to continue to work properly when this interfering signal is 65 dB stronger than the desired signal.
Regarding current demodulation techniques, one of the more recently researched that of a xcex94xcexa3PLL demodulator. A generalized schematic of this approach is illustrated in FIG. 1. The principle of operation here is that the circuit is a xcex94xcexa3 modulator. When considered this way, the dual modulus divider (n/n+d) and phase detector (PD) provide the first integrator of a xcex94xcexa3 modulator. This assertion can be justified by considering that the phase detector detects phase which is inherently the integral of the divider output frequency. The two charge pumps (CP) then provide the second integration stage for a second order xcex94xcexa3 modulator.
The amount of quantisation noise in the output bit stream for second order noise shaping depends on the reference frequency, fS, and the step size of the divider, xcex4. In general, the divider can divide by n or n+xcex4 where xcex4 might be less than 1. The spectral density of the quantisation error is given approximately by                     δ                              12                    ⁢                      f            s                              ⁢                        (                      1            -                          z                              -                1                                              )                2              "RightBracketingBar"                                =          exp                )            ⁢      j2      ⁢              xe2x80x83            ⁢      Π      ⁢              xe2x80x83            ⁢              fT        s              )  
and the full scale input range for the FM deviation is xcex4fs. This is a high pass function which places zeros in the noise at dc. Other noise shaping functions are possible and discussed in the xcex94xcexa3 modulator literature.
In general the quantizer need not be restricted to a single bit quantizer. In this case, the output is a multibit digital word, however we still refer to it as a bit stream. The full scale deviation is then pxcex4fs where p is one greater than the number of digital levels in the bit stream. However, the demodulator of FIG. 1 can also be seen as a PLL. From this PLL point of view, the dual modulus divider (n/n+xcex4) is like a VCO. Applying more 1""s to the divider control input (c) causes the divider to divide by the larger modulus more often and, as a result, to have a lower output frequency. The phase of this divider output is sampled relative to the reference frequency in the phase detector (PD). This sampling occurs at the divider output frequency and is integrated in the first charge pump (CP) loop filter. A second charge pump feeding back from the quantiser provides the stabilizing zero necessary for stability in a second order PLL. The presence of the quantiser in this PLL, however, complicates the PLL analogy and as a result the circuit is not often presented from this point of view.
Regardless of whether or not we find it more useful to regard the demodulator as a PLL, the resulting bit stream can then be processed either with digital filtering or analog filtering. If the bit stream is analog filtered with two or more poles in the filter, the high frequency noise can be rolled off to result in a white noise at some low level. It can then be passed directly to the speaker driver.
The primary limitation with this type of demodulator is that the input signal must be sufficiently band limited to remove interfering signals. As well, the signal must be hard limited before entering the demodulator. A practical reason for these requirements is that the input frequency is used to clock the digital logic making up the divider. Under these conditions, the signal must be filtered to the point where the zero crossings of the input signal are substantially unchanged by an interfering signal. In other words, the selectivity must come before the xcex94xcexa3 demodulator. This offers no hope of reducing the cost of the IF filter although it does offer a means of demodulation in a single IC.
Another way of looking at the need to filter before entering this demodulator is that both the divider and the edge triggered phase detector can process only information which is contained in the zero crossings of the input signal. In the presence of a strong interferer, the zero crossings are dominated by this interferer, and the demodulator phase locks to the interfering signal. With a very large interferer, the small signal simply rides on top of the interferer and causes only a few zero crossings. As a result, the desired signal can be extracted only by looking at the amplitude information as well. With this theoretical consideration in mind, it seems unfortunate that the original xcex94xcexa3 FM demodulators as in FIG. 1 threw away the amplitude information at the extreme front end of the demodulator.
One approach to demodulation and filters which is most helpful is to consider complex valued signals. The approach taken here is to show that simple phasors are used to describe real signals. This concept of phasors is then extended to include the concept of complex envelope for a bandpass signal. Neither of these constitute a complex signal even though they are complex representations of a real signal.
To take a simple example of the use of phasors, assume we want to find the sum of two voltages that are both sinusoidal functions of time.
xe2x80x83s(t)=A1 cos (xcfx89ct+xcfx861)+A2 cos (xcfx89ct+xcfx862)
To avoid the process of summing up sinusoids in the time domain, each of the sinusoids above can be expressed in complex exponential form i.e.       cos    ⁢          xe2x80x83        ⁢    θ    =                              ⅇ                      j            ⁢                          xe2x80x83                        ⁢            θ                          +                  ⅇ                                    -              j                        ⁢                          xe2x80x83                        ⁢            θ                              2        =          Re      ⁢              {                  ⅇ                      j            ⁢                          xe2x80x83                        ⁢            θ                          }            
From the above, it is clear that the imaginary part of ejxcex8 will always cancel with the imaginary part of exe2x88x92jxcex8 and that the real part is in fact cosxcex8. Similarly, the sum of two sinusoids then becomes                                                         A              1                        ⁢                          cos              ⁡                              (                                                                            ω                      c                                        ⁢                    t                                    +                                      ϕ                    1                                                  )                                              +                                    A              2                        ⁢                          cos              ⁡                              (                                                                            ω                      c                                        ⁢                    t                                    +                                      ϕ                    2                                                  )                                                    =                ⁢                                            A              1                        ⁢                          xe2x80x83                        ⁢                                                            ⅇ                                                            j                      ⁢                                              xe2x80x83                                            ⁢                                              ω                        c                                            ⁢                      t                                        +                                          ϕ                      ⁢                                              xe2x80x83                                            ⁢                      I                                                                      +                                  ⅇ                                                                                    -                        j                                            ⁢                                              xe2x80x83                                            ⁢                                              ω                        c                                            ⁢                      t                                        +                                          ϕ                      1                                                                                  2                                +                                                ⁢                              A            2                    ⁢                                                    ⅇ                                                      j                    ⁢                                          xe2x80x83                                        ⁢                                          ω                      c                                        ⁢                    t                                    +                                                            ϕ                      ⁢                                              xe2x80x83                                                              2                                                              +                              ⅇ                                                                            -                      j                                        ⁢                                          xe2x80x83                                        ⁢                                          ω                      c                                        ⁢                    t                                    +                                      ϕ                    2                                                                        2                                                  =                ⁢                              1            2                    [                                    (                                                                    A                    1                                    ⁢                                      ⅇ                                                                  j                        ⁢                                                  xe2x80x83                                                ⁢                                                  ω                          c                                                ⁢                        t                                            +                                                                        ϕ                          ⁢                                                      xe2x80x83                                                                          1                                                                                            +                                                      A                    2                                    ⁢                                      ⅇ                                                                  xe2x80x83                                            ⁢                                                                        j                          ⁢                                                      xe2x80x83                                                    ⁢                                                      ω                            c                                                    ⁢                          t                                                +                                                                              ϕ                            ⁢                                                          xe2x80x83                                                                                2                                                                                                                                )                        +                                                          ⁢                  (                                                    A                1                            ⁢                              ⅇ                                                      xe2x80x83                                    ⁢                                      (                                                                  j                        ⁢                                                  xe2x80x83                                                ⁢                                                  ω                          c                                                ⁢                        t                                            +                                                                        ϕ                          ⁢                                                      xe2x80x83                                                                          1                                                              )                                                                        +                                          A                2                            ⁢                              ⅇ                                                      xe2x80x83                                    ⁢                                                                                    -                        j                                            ⁢                                              xe2x80x83                                            ⁢                                              ω                        c                                            ⁢                      t                                        +                                                                  ϕ                        ⁢                                                  xe2x80x83                                                                    2                                                        )                                                              )                ]            
Here, the third line groups the sum into two positive frequency exponentials and the sum of two negative frequency exponentials. Again since the sum of two real signals must be another real signal, we would expect that the imaginary parts would cancel out. Some inspection of the equations will reveal that this is true. The convenience of phasor notation comes when we decide to ignore the negative frequency components. Since the imaginary parts of the sum cancel out, and the real parts of the positive frequency components are equal to the real parts of the negative frequency components, we can see that
A1 cos(xcfx89ct+xcfx861)+A2 cos(xcfx89ct+xcfx862)=Re{(A1ejxcfx861+A2ejxcfx862)ej2xcfx80fct}
Thus for example, in a 50 Hz transformer (fc=50 Hz) we get all the information we need from looking at only the term in brackets.
A1ejxcfx861+A2ejxcfx862
This is the well known phasor addition of the two sinusoids that we started with. By further ignoring the common factor of ej2xcfx80fc1, the time dependency has been eliminated and only complex constants remain. Note that we end up with fixed constants for the term in brackets (the phasor) because all the signals we are looking at are at the same frequency, fc.
The phasor concept can be extended to the complex envelope of a bandpass signal. Suppose that we let each of the phase offsets in the previous phasor example be a function of time, xcfx86(t),                               If          ⁢                      xe2x80x83                    ⁢                      ϕ            ⁡                          (              t              )                                      =                                            (                                                ω                  c                                +                                  ω                  1                                            )                        ⁢            t            ⁢                          xe2x80x83                        ⁢            and            ⁢                          xe2x80x83                        ⁢                                          ϕ                2                            ⁡                              (                t                )                                              =                                    (                                                ω                  c                                +                                  ω                  2                                            )                        ⁢            t                              ,              
            ⁢              then        ⁢                  xe2x80x83                ⁢        the        ⁢                  xe2x80x83                ⁢        sum        ⁢                  xe2x80x83                ⁢        of        ⁢                  xe2x80x83                ⁢        two        ⁢                  xe2x80x83                ⁢        sin        ⁢                  xe2x80x83                ⁢        usoids        ⁢                  xe2x80x83                ⁢        is              ⁢          xe2x80x83                          A        1            ⁢              cos        ⁡                  (                                                    ω                c                            ⁢              t                        +                                          ω                1                            ⁢              t                                )                      +                  A        2            ⁢              cos        ⁡                  (                                                    ω                c                            ⁢              t                        +                                          ω                c                            ⁢              t                                )                                                              The            ⁢                          xe2x80x83                        ⁢            complex                    =                    ⁢                                    1              2                        [                                                            (                                                                                    A                        1                                            ⁢                                              ⅇ                                                  j                          ⁢                                                      xe2x80x83                                                    ⁢                                                      ω                            1                                                    ⁢                          t                                                                                      +                                                                  A                        2                                            ⁢                                              ⅇ                                                  j                          ⁢                                                      xe2x80x83                                                    ⁢                                                      ω                            2                                                    ⁢                          t                                                                                                      )                                ⁢                                  ⅇ                                      j                    ⁢                                          xe2x80x83                                        ⁢                    2                    ⁢                                          xe2x80x83                                        ⁢                    π                    ⁢                                          xe2x80x83                                        ⁢                                          f                      c                                        ⁢                    1                                                              +                                                                              ⁢                                    (                                                                    A                    1                                    ⁢                                      ⅇ                                                                  -                        j                                            ⁢                                              xe2x80x83                                            ⁢                                              ω                        1                                            ⁢                      t                                                                      +                                                      A                    2                                    ⁢                                      ⅇ                                                                  -                        j                                            ⁢                                              xe2x80x83                                            ⁢                                              ω                        2                                            ⁢                      t                                                                                  )                        ⁢                          ⅇ                                                -                  j                                ⁢                                  xe2x80x83                                ⁢                2                ⁢                                  xe2x80x83                                ⁢                π                ⁢                                  xe2x80x83                                ⁢                                  f                  c                                ⁢                t                                              ]                    
envelope of the sum of the two sinusoids is just the term.
A1ejxcfx891t+A2ejxcfx892t
Where the same term produced a static complex number for the phasor, the sum of two sinusoids of differing frequencies produced a complex value that is a function of time. We can now use a complex mathematical representation but the signal stays real. As with phasors, it is again possible to ignore both the negative frequency components and the carrier frequency, f. This type of analysis is routinely carried out in digital communications texts. If two sinusoids are summed, the phasors of each sinusoid are now functions of time and rotate relative to the carrier frequency.
The addition of two sinusoids results in the expected AM modulated sinusoid at a new frequency. The frequency of the AM modulation is given by the difference in frequency between the two sinusoids we are summing. The simple concept of envelope commonly seen on an oscilloscope relates to the amplitude of the AM modulation which is quite visible in the upper sinusoid. That is, at any point in time there is an envelope shown with a dotted line. The new concept which extends the old familiar concept of an envelope is to also look at the phase of the upper sinusoid relative to the phase of some arbitrarily chosen carrier frequency and phase. By having an amplitude and a phase, we have the polar representation of a complex signal. As with any complex signal, the magnitude and phase can also be represented as inphase and quadrature components.
However, clearly, the world we live in doesn""t have any j operators and thus there are no true complex signals. However, many circuits contain two real signals that we would like to behave the same way as one complex signal. One way to define complex signal is to describe a way to make one.
An obvious example of use to radio work is a In-phase and Quadrature downconverter. FIG. 2(a) shows a standard block diagram for an xe2x80x9cIn-phasexe2x80x9d and Quadrature mixer. FIG. 2(c) shows an abstract mathematical modem for same mixer.
To get the abstract model of the hardware, we can use a transitional model, shown in FIG. 2(b). To get this model, we need only to believe that j means xe2x80x9cthe other wirexe2x80x9d and from then on we can think of X=I+jQ as one complex signal rather than two real signals. The j operator in the middle figure allows us to mathematically add the two signals to obtain FIG. 2(b) while keeping the I and Q channels separate. This addition has no corresponding component in either the hardware or the abstract model but it is fundamental to the understanding of complex filters from the point of view presented here. The transitional model, showing this addition, is therefore particularly useful because it allows recognition of the hardware in the block diagram while at the same time providing the abstract model through mathematical manipulations.
By thinking of the two real signals as one complex signal, it becomes easier to design filters for the two signals. The motive for filtering two real signals is conceptually related to the motive for using phasors or complex envelopes. Just as using a complex envelope simplifies the mathematical analysis of a real high frequency signal, the filtering of two real signals (which we hope represent the high frequency signal) can be simpler to construct than a filter for the original high frequency signal.
To represent a complex signal, at least two real signals are required. Additional signals can provide redundancy and more robust implementations. For example, if both the inphase signal and the quadrature signal are provided with their complimentary (180xc2x0 phase shifted) counter parts, then there are four signals and balanced circuit techniques can be used to improve power supply rejection ratio. Similarly, the use of other redundant signals phase shifted by multiples of 45xc2x0 or 5xc2x0, for example, may provide other opportunities for more robust embodiments of complex filters. Thus, a complex signal is in general represented by a plurality of real signals.
Another technique for generating complex signals is the Hilbert Transform or Hilbert Filter. An ideal Hilbert filter rejects all negative frequency exponentials while passing positive frequency exponentials. That is, given a real input (composed of equally weighted positively rotating exponentials and negatively rotating exponentials), a Hilbert Filter provides a complex output (composed of only the positively rotating exponentials). Another way of looking at the same thing is to say that the output must have a real channel with the original input signal and an imaginary channel with each sinusoidal component of the input phase shifted by exactly 90 degrees. When looking at it this way, the ideal Hilbert filter is more commonly called the Hilbert transform.
One can simply consider the Hilbert transform or Hilbert Filter as a special case of a more general class of filters called complex filters. The distinguishing feature of such filters is that they have a different frequency response for positively rotating exponentials than for negatively rotating exponentials. Thus a real input can produce a complex output by substantially removing for example, negatively rotating exponentials.
The above are not the only methods of obtaining complex signals. Complex signals can also be obtained by sampling. FIG. 3A shows an example where an IF signal is sub-sampled with a small time shift in the quadrature sample. P1 and P2 are phases that tell the Track and Hold amplifiers to hold their input value when the phases P1 or P2 are high. P3 then samples the held values coming out of the track and hold amplifiers on the falling edge of P3. FIG. 3B shows the timing diagrams associated with the circuit of FIG. 3A.
We can now consider an example where the P1 and P2 phases have an offset, xcex94T; of xc2xe of the IF period and a sampling period, T, equal to 10 cycles of the nominal IF frequency. Specifically, for a 45 MHz nominal IF frequency we are sampling at 4.5 MHz and xcex94T=4/(135 MHz)=29.6 ns. FIG. 4 shows the voltages sampled onto the holding capacitors for an input frequency slightly faster than 45 MHz. By visualizing these samples as components of a complex number, we can see that they represent a positively rotating complex exponential. This is illustrated by the timing diagrams of FIG. 4.
Both the I channel and the Q channel display familiar aliasing behavior and the sampling produces a downconversion through this aliasing. It can also be seen that the I channel follows a low frequency cosine function while the Q channel follows a low frequency sine function. Thus, I+jQ follows a positively rotating complex exponential.
Now that complex signals can be obtained, they can also be used in a PLL. When so used, a complex valued phase locked loop (CVPLL) is obtained. A complex-valued PLL (CVPLL) can be analyzed in terms of FIG. 5 below. The incoming signal can be Hilbert transformed by either an inphase and quadrature downconversion or by a complex filter or a combination of both. The result will be a complex exponential represented by two real signals with some impairments depending on the accuracy of the Hilbert transform. A second component of the PLL is a VCO which produces an inphase and quadrature output. This output can be thought of as another complex exponential which we wish to phase lock to the incoming complex exponential from the Hilbert transform. The last component is a full complex multiplier which is used as a phase detector and amplitude demodulator.
The operation of the PLL can be understood by ignoring, for now, the hardware and studying the mathematical operations the circuit is intended to perform. The Hilbert transform (which may include a downconversion not shown in the figure) will give us two signals, I and Q representing the phasor of the incoming signal. Mathematically, this phasor can be expressed in either Cartesian form, I+jQ, or polar form, Aejxcex8. FIG. 5 shows the polar form of the signal because the phase we wish to lock in this PLL is the phase angle of the complex number. More specifically, the VCO also has a phase angle for its complex exponential output which we want to phaselock to the incoming signal. Mathematically, the way this happens is that the VCO carrier frequency and the incoming carrier frequency terms cancel out in the complex multiplication leaving only a small signal xcfx86(t) to control the VCO frequency. Since the phase of the VCO depends on the integral of xcfx86(t), xcfx86(t) must be small when the loop is locked.
One of the features of the CVPLL is that this loop band-width can be higher than the carrier frequency of the signal it is trying to lock to. The reason for this is that the phase detector provides a continuous indication of the phase error without the usual double frequency components of conventional PLLs. The continuous signal from the phase detector continuously corrects the VCO input voltage to produce the correct frequency and phase.
Both the xcex94xcexa3 PLLs and the CVPLLs above are forms of broad band PLL capable of rapid acquisition and FM demodulation. The xcex94xcexa3 PLLs provide high bandwidth by working in discrete time and oversampling the bandwidth of the modulated signal. The CVPLLs provide high bandwidth by using continuous time feedback to the VCO. In the xcex94xcexa3 PLLs, the demodulated FM output comes from the bit stream which can be low pass filtered to recover the original FM modulated signal. In the CVPLLs the demodulated FM output is available from the VCO input.
Although the xcex94xcexa3PLLs have the advantage of requiring no precision components, they require extensive filtering in front of the demodulator at the intermediate frequency. The phase response of this filter reduces the linearity of the overall demodulator. It is also expensive to obtain narrow band temperature-stable filters to meet these requirements at higher intermediate frequencies.
The CVPLLs have the advantage of retaining both the amplitude and phase information of the incoming signal. This allows further processing of the signal after it is demodulated. One difficulty for the CVPLL when used in an integrated circuit is that a low noise VCO can be difficult to obtain on chip. A continuous time VCO can also be vulnerable to interference from repetitive or pseudo-random digital signals on the same chip. Another difficulty is that the linearity of the demodulator is limited by the linearity of the VCO tuning characteristic.
The present invention avoids the shortcomings of the prior art as discussed above by providing a complex valued delta sigma Phase Locked Loop (PLL) demodulator. The demodulator is a multiple stage demodulator. The first stage is a conversion stage which converts an incoming signal into a first complex representation. The second stage is a direct digital synthesizer (DDS)/mixer which synthesizes a signal to be mixed with the first complex signal and performs the mixing operation to produce a second complex output. This second complex signal is controlled by a bitstream fed back from the third stagexe2x80x94a phase quantizer stage. The bitstream represents the quantized phase difference between the synthesized signal and the first complex signal. The DDS/mixer stage then measures the synthesized signal for any phase difference from the incoming signal through the feedback inherent to a PLL, the bitstream thus provides an output that gives the frequency of the desired signal. As a side benefit, the real component of the second complex signal, provides an amplitude estimate of the desired signal.
In a first embodiment the present invention provides a multiple stage frequency demodulator which demodulates an input frequency modulated (FM) signal and produces a bitstream output and the demodulator comprising:
a conversion stage which receives said input signal and which produces a first intermediate complex signal representing the input signal;
a mixer stage which receives said first intermediate complex signal from said conversion stage and said bitstream output as a feedback signal, said mixer stage producing a second intermediate complex signal; and
a phase quantizer stage which receives said second intermediate complex signal, said phase quantizer stage producing said bitstream output; wherein
said mixer stage performs a discrete phase shift on said first intermediate complex signal, said phase shift being proportional to a value of said bitstream output;
said phase quantizer determines a phase angle of the second intermediate complex signal; and
said phase quantizer produces said bitstream output based on whether said phase angle lags or leads the phase of a predetermined signal.
In a second embodiment the present invention provides a Hilbert sampler/filter circuit comprising:
a circuit element having a transconductance;
a plurality of sampler cells, each sampler cell comprising:
a buffer coupled to a transmission switch;
a sampler switch coupled between the circuit element and the buffer;
a capacitor coupled between ground and a first connection point;
a grounding switch coupled between the first connection point and ground; and
a second connection point located between the sampler switch and the buffer, said second connection point also being coupled to the first connection point;
wherein for the plurality of sampler cells, only one sampler switch is closed during any one time interval.
In a third embodiment the present invention provides a Hilbert sampler/filter circuit comprising:
a grounding switch;
an array of coupling switches;
a circuit element having a transconductance;
a plurality of sampler cells, each sampler cell being coupled to both the circuit element and the grounding switch at a common node; and
a plurality of filter cells; wherein
the grounding switch, when closed, couples said circuit element and each sampler cell to ground;
each secondary sampler cell can be cupled to any of the primary sampler cells using the array of coupling switches.
In a fourth embodiment the present invention provides a sampler/filter circuit comprising:
a circuit element having a transconductance;
a plurality of sampler cells, each sampler cell comprising:
an operational amplifier coupled between a first sampler and a second sampler node;
a sampling switch coupled between the circuit element and the second sampler node;
a sampling capacitor coupled between the circuit element and the second sampler node;
a sampling capacitor coupled between the second sampler node and ground;
a pair of primary switches, one primary switch being coupled between a third sampler node and ground and the other primary switch being coupled between a fourth sampler node and ground;
a pair of secondary switches, one secondary switch coupled between the third sampler node and the second sampler node, and the other secondary switch being coupled between the fourth sampler node and the first sampler node;
a filtering capacitor coupled between the third sampler node an the fourth sampler node; wherein
the first sampler node is between a sampler cell output and an output of the operational amplifier;
the second sampler node is coupled to the negative input of the operational amplifier;
the positive input of the operational amplifier is coupled to a predetermined reference voltage;
both primary switches are switched simultaneously;
both secondary switches are switched simultaneously.
In a fifth embodiment the present invention provides a sampler/filter circuit comprising at least one pair of sampler cells such that each pair of sampler cells comprising:
a first and a second sampling switch, the first sampling switch being coupled between a first intermediate node and an input and the second sampling switch being coupled between the input and a second intermediate node;
a first and a second operational amplifier, the first operational amplifier being coupled between the first intermediate node and a first output node, the second operational amplifier being coupled between the second intermediate node and a second output node;
a pair of primary sampling capacitors, one primary sampling capacitor being coupled between the first intermediate node and a third intermediate node, the other primary sampling capacitor being coupled between the second intermediate node and a fourth intermediate node;
a pair of secondary sampling capacitors, one secondary sampling capacitor being coupled between the first intermediate node an a fifth intermediate node, the other secondary sampling capacitor being coupled between the second intermediate node and a sixth intermediate node;
a pair of filtering capacitors, one filtering capacitor being coupled between a negative input of the first operational amplifier and the first output node, the other filtering capacitor being coupled between a negative input of the second operational amplifier and the second output node;
for primary switches, each primary sampling switch being placed in the sampler cells such that a primary sampling switch is coupled between ground and each of the third, fourth, fifth and sixth intermediate nodes;
a negator for changing the polarity of a signal, said negator being coupled to the first output node;
four secondary sampling switches, said secondary switches being coupled such that:
a first secondary sampling switch being coupled between the third intermediate node and the first output node;
a second secondary sampling switch being coupled between the fourth intermediate node and the second output node;
a third secondary sampling switch being coupled between the fifth intermediate node and the second output node;
a fourth secondary sampling switch being coupled between the negator and the sixth intermediate node;
wherein
the negative input of the first operational amplifier is coupled to the first intermediate node;
the negative input of the second operational amplifier is coupled to the second intermediate node;
the positive input of both operational amplifiers is coupled to ground;
all primary sampling switches are switched simultaneously;
all secondary sampling switches are switched simultaneously.
In a sixth embodiment the present invention provides a direct digital synthesizer/mixer circuit receiving a first intermediate complex signal and a bitstream as input, the circuit comprising:
a frequency synthesizer producing at least one mixer signal having a frequency dependent on the bitstream input;
a mixer which mixes at least one mixer signal to the first intermediate complex signal; where
the synthesizer/mixer circuit produces a second intermediate complex signal; and
the at least one mixer signal, when mixed with the first intermediate signal, minimizes a phase difference between the first intermediate complex signal and the second intermediate complex signal.
In a seventh embodiment the present invention provides a method of demodulating an input signal to produce a bitstream output, the method comprising:
a) receiving the input signal,
b) producing a first intermediate complex signal representing the input signal, said first intermediate complex signal having an inphase component and a quadrature component,
c) shifting the phase of the first intermediate complex signal in response to the bitstream output to produce a second intermediate complex signal,
d) determining a phase angle of the second intermediate complex signal,
e) producing the bitstream output by outputting a specific bit if the phase angle lags or leads a predetermined signal.
In an eighth embodiment the present invention provides a method of sampling an input signal, the method comprising:
a) receiving the input signal at a plurality of sampler cells, each sampler cell having a sampling switch for sampling the input signal;
b) sequentially closing the sampling switch at each sampler cell for a fixed time interval to sample the input signal at different instances; wherein only one sampling switch is closed during any one time interval.
In a ninth embodiment the present invention provides a sampler/filter circuit comprising:
a plurality of sampler cells, each sampler cell comprising:
an operational amplifier coupled between a first sampler and a second sampler node;
a sampling switch coupled between the circuit element and the second sampler node;
a sampling capacitor coupled between the circuit element and the second sampler node;
a sampling capacitor coupled between the second sampler node and ground;
a pair of primary switches, one primary switch being coupled between a third sampler node and ground and the other primary switch being coupled between a fourth sampler node and ground;
a pair of secondary switches, one secondary switch coupled between the third sampler node and the second sampler node, and the other secondary switch being coupled between the fourth sampler node and the first sampler node;
a filtering capacitor coupled between the third sampler node an the fourth sampler node; wherein
the first sampler node is between a sampler cell output and an output of the operational amplifier;
the second sampler node is coupled to the negative input of the operational amplifier;
the positive input of the operational amplifier is coupled to a predetermined reference voltage;
both primary switches are switched simultaneously;
both secondary switches are switched simultaneously.
In a tenth embodiment the present invention provides a sampler/filter circuit comprising:
a plurality of sampler cells, each sampler cell comprising:
a buffer coupled to a transmission switch;
a sampler switch coupled between an input and the buffer;
a capacitor coupled between ground and a first connection point;
a grounding switch coupled between the first connection point and ground; and
a second connection point located between the sampler switch and the buffer, said second connection point also being coupled to the first connection point;
wherein for the plurality of sampler cells, only one sampler switch is closed during any one time interval.
In an eleventh embodiment the present invention provides a sampler/filter circuit comprising:
a grounding switch;
an array of coupling switches;
a plurality of sampler cells, each sampler cell being coupled to both an input and the grounding switch at a common node; and
a plurality of filter cells;
wherein
the grounding switch, when closed, couples each sampler cell to ground;
each secondary sampler cell can be coupled to any of the primary sampler cells using the array of coupling switches.